Embodiments of the invention relate to methods and systems for processing interrupts in a computing system. In particular, embodiments of present invention relate to reducing the computational penalty associated with processing interrupts.
An interrupt is an event that alters the sequence in which a processor executes instructions An interrupt unit may interrupt a current process executing a sequence of instructions to execute one or more higher-priority instructions. Once the interrupt sub-routine is processed, the processor may return from the interrupt sub-routine and resume processing the initial sequence of instructions.
The sequence of instructions may include a branch instruction. A branch instruction may cause a process to proceed in one of multiple possible ways, e g , based on a branch condition. For example, in a sequence of instructions, 1, 2, 3, 4, 5, where 5 is a branch instruction, instruction 5 may cause the process to proceed sequentially to instructions 6, 7, 8, . . . or to jump to instructions 100, 101, 102, . . . The instruction following the branch instruction, e.g., 6 or 100, may be unknown until the branch instruction is executed.
A branch predictor may be used to predict the outcome of a conditional branch. The predicted instructions at the branch may be preemptively retrieved from program memory and temporarily stored in a program cache for easy access. The branch prediction may be correct or incorrect. The branch predictor may resolve the branch outcome and determine if the branch prediction is correct or incorrect over one or more subsequent computational cycles. When an interrupt occurs during the computational cycles used to resolve the branch, the branch outcome is unknown and must be re-computed.
A branch instruction may be associated with one or more subsequent delay slots When an interrupt is accepted following a branch instruction, the interrupt may be processed in one of the delay slots. The branch condition to determine if the prediction is correct or not may be computed during the same computational cycles in which the delay slots are processed. Therefore, when an interrupt occurs during a delay slot of a branch instruction and is processed by replacing the delay slot, the outcome of the branch condition computation may be unknown. Accordingly, branch instructions and instruction processed in the associated delay slots cannot be properly executed and must be re-processed after the interrupt is handled and the initial instructions resume.
Typically it is not known if an instruction is a branch instruction until the instruction has been decoded, e.g., after processing the instructions for several computational cycles In current systems, instructions which are not yet decoded are indiscriminately discarded prior to decoding, just in case, but before it is known if, the instructions are branch instructions. The additional computational cycles used to re-process the discarded data may be referred to as an interrupt penalty. Accordingly, an interrupt penalty is always incurred when processing an interrupt.